Ultra-short-height standard cell architecture

A device, comprising:

• a substrate comprising an integrated circuit comprising a standard cell, wherein the standard cell comprises a first cell boundary and a second cell boundary, wherein the standard cell comprises a three-track cell height defined by a distance between the first cell boundary and the second cell boundary;
• a first interconnect structure disposed on a first side of the substrate, wherein the first interconnect structure comprises a first signal track, a second signal track, and a third signal track, which are disposed in parallel within an area of the integrated circuit between the first cell boundary and the second cell boundary of the standard cell;
• and
• a second interconnect structure disposed on a second side of the substrate, opposite the first side, wherein the second interconnect structure comprises a fourth signal track, a fifth signal track, a first power distribution track, and a second power distribution track, which are disposed in parallel within the area of the integrated circuit between the first cell boundary and the second cell boundary of the standard cell.

A computer program product, comprising:

• one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instructions comprising:
• program instructions to define a standard cell library comprising at least one three-track standard cell which comprises a first cell portion and a second cell portion, wherein the first cell portion is configured to be disposed on a first side of a substrate, and the second cell portion is configured to be disposed on a second side of the substrate, opposite the first side of the substrate, in alignment with the first cell portion, wherein the first cell portion and the second cell portion of the at least one three-track standard cell each comprise respective cell boundaries which are aligned to each other on the opposite first and second sides of the substrate, and which define a first cell boundary and a second cell boundary of the at least one three-track standard cell, wherein the at least one three-track standard cell comprises a three-track cell height defined by a distance between the first cell boundary and the second cell boundary;
• and
• program instructions to utilize the at least one three-track standard cell to generate a layout of a semiconductor integrated circuit device comprising the at least one three-track standard cell.