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US 12,001,768 B1Granted
Enhanced glitch estimation in vectorless power analysis
AssigneeSynopsys, Inc.
InventorsQing Su, Pankaj Singla, Solaiman Rahim, Eduard Petrus Huijbregts, Stephan Houben
Life of this patent
Estimating the term…
Abstract
A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.
Claims18
A method, comprising:
- acquiring timing analysis data associated with a cell of a design of an integrated circuit and activity data of one or more inputs of the cell;
- determining, by a processor, a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, wherein the determining the glitch toggle rate comprises:
- computing a total toggle rate for the cell using a stochastic simulation, based on static probabilities and toggle rates of the one or more inputs of the cell and based on an inertial delay of the cell;
- computing a functional toggle rate based on the one or more inputs of the cell;
- and
- computing the glitch toggle rate based on the total toggle rate and the functional toggle rate;
- adjusting the glitch toggle rate based on a correction term for two or more simultaneous toggles on inputs of the cell;
- and
- estimating, by the processor, a glitch power of the design of the integrated circuit based on at least the glitch toggle rate.
6 more elements
A system, comprising:
- a memory storing instructions;
- and
- a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
- acquire timing analysis data associated with a cell of a design of an integrated circuit and activity data of one or more inputs of the cell;
- determine a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs and the timing analysis data, wherein the determining the glitch toggle rate comprises:
- compute a total toggle rate for the cell using a stochastic simulation, based on static probabilities and toggle rates of the one or more inputs of the cell and based on an inertial delay of the cell;
- compute a functional toggle rate based on the one or more inputs of the cell;
- and
- compute the glitch toggle rate based on the total toggle rate and the functional toggle rate;
- adjust the glitch toggle rate based on a correction term for two or more simultaneous toggles on inputs of the cell;
- and
- estimate a glitch power of the design of the integrated circuit based on at least the glitch toggle rate.
9 more elements
A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
- acquire timing analysis data associated with a cell of a design of an integrated circuit and activity data of one or more inputs of the cell;
- determine a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs and the timing analysis data, wherein the determining the glitch toggle rate comprises:
- computing a total toggle rate for the cell using a stochastic simulation, based on static probabilities and toggle rates of the one or more inputs of the cell and based on an inertial delay of the cell;
- computing a functional toggle rate based on the one or more inputs of the cell;
- and
- computing the glitch toggle rate based on the total toggle rate and the functional toggle rate;
- adjust the glitch toggle rate based on a correction term for two or more simultaneous toggles on inputs of the cell;
- and
- estimate a glitch power of the design of the integrated circuit based on at least the glitch toggle rate.
6 more elements
Dependencies are inferred from the claim text.