Memory with virtual page size

An electronic memory apparatus, comprising:

• a memory array that includes a plurality of row access lines that are each coupled with a row of memory cells of the memory array and a plurality of column access lines that are each coupled with a column of memory cells of the memory array;
• and
• a memory controller coupled with the plurality of row access lines and the plurality of column access lines, wherein the memory controller is operable to:
• receive a request to access one or more memory cells of the memory array;
• send, to the memory array, a first command to identify a set of memory cells of the memory array based at least in part on the request, wherein the set of memory cells comprises a first quantity of memory cells corresponding to a nominal page size of the memory array, the first quantity of memory cells comprising one or more subsets of memory cells each comprising a second quantity of memory cells corresponding to an internal page size of the memory array and each associated with one or more access operations, wherein the first quantity of memory cells remain deactivated based at least in part on receiving the first command;
• send, to the memory array and based at least in part on sending the first command to identify the set of memory cells, one or more second commands to activate a first subset of the set of memory cells and a second subset of the set of memory cells, wherein the first subset and the second subset each comprise the second quantity of memory cells corresponding to the internal page size of the memory array, wherein the nominal page size is an integer multiple of the internal page size, and wherein the internal page size is a variable page size and is based at least in part on receiving the request to access the one or more memory cells of the memory array;
• and
• access at least one memory cell of the first subset and at least one memory cell of the second subset in response to the request.

An apparatus, comprising:

• means for receiving a request to access one or more memory cells of a memory array;
• means for sending, from a memory controller of the apparatus to a memory array comprising a plurality of row access lines and a plurality of column access lines coupled with memory cells of the memory array and the memory controller, a first command to identify a set of memory cells of the memory array based at least in part on the request, wherein the set of memory cells comprises a first quantity of memory cells corresponding to a nominal page size of the memory array, the first quantity of memory cells comprising one or more subsets of memory cells each comprising a second quantity of memory cells corresponding to an internal page size of the memory array and each associated with one or more access operations, wherein the first quantity of memory cells remain deactivated based at least in part on receiving the first command;
• means for sending, to the memory array and based at least in part on sending the first command to identify the set of memory cells, one or more second commands to activate a first subset of the set of memory cells and a second subset of the set of memory cells, wherein the first subset and the second subset each comprise the second quantity of memory cells corresponding to the internal page size of the memory array, wherein the nominal page size is an integer multiple of the internal page size, and wherein the internal page size is a variable page size and is based at least in part on receiving the request to access the one or more memory cells of the memory array;
• and
• means for accessing at least one memory cell of the first subset and at least one memory cell of the second subset in response to the request.