Data transfer in port switch memory
OwnerFrank F. Rossinventor
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.
Claims17
An apparatus, comprising:
- a first number of memory devices coupled to a host via a first number of ports;
- and
- a second number of memory devices coupled to the first number of memory devices via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices via the second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host during a same clock cycle that the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices.
An apparatus, comprising:
- memory module, wherein the memory module includes a first number of memory devices and a second number of memory devices coupled to a controller, wherein the memory module is coupled to a host, and wherein the memory module is configured to:
- receive a first number of commands for execution on a first portion of the first number of memory devices via a first number of ports;
- and
- receive a second number of commands for execution on a second portion of the first number of memory devices on the memory module via the first number of ports wherein a multiplexor is configured to isolate the second portion of the first number of memory devices from the host in response to memory module receiving the second number of commands.
A method, comprising:
- receiving, from a host device, a first command via a first port of a first memory die of a memory device on a memory module, wherein the memory device comprises a first bus coupled between the first port and the host device and a second bus coupled between a second port of the first memory die and a controller of the memory module;
- receiving, from the controller of the memory module, a second command via a second port of a second memory die of the memory device, wherein a first port of the second memory die is coupled to the first bus of the memory device and the second port of the second memory die is coupled to the second bus of the memory device;
- and
- executing the first command at the first memory die of the first device and the second command at the second memory die of the first device, wherein first memory die and the second memory die are paired together via the first port and second port and wherein the second memory die is isolated from the host device by a multiplexor and the first port.
Dependencies are inferred from the claim text.