Memory system and method to configure logical blocks

A memory system comprising:

• a non-volatile memory including a plurality of memory chips including one or more first memory chips, each first memory chip including a plurality of physical blocks and one or more second memory chips, each second memory chip including a plurality of physical blocks, each memory chip configured to operate independently;
• and
• a controller configured to communicate with a host and control the non-volatile memory,
• wherein the controller is configured to:
• configure a first logical block by parallelizing the physical blocks of each of the one or more first memory chips and the physical blocks of each of the one or more second memory chips in an interleaved configuration so that the physical blocks of each of the one or more first memory chips and the physical blocks of each of the one or more second memory chips can be used simultaneously;
• generate a second logical block from the physical blocks of the first memory chip;
• generate a third logical block from the physical blocks of the second memory chip;
• divide the physical blocks of each of the one or more first memory chips into a group for the first logical block and a group for the second logical block;
• and
• divide the physical blocks of each of the one or more second memory chips into a group for the first logical block and a group for the third logical block.