Storage biasing for solid state drive accelerators

A method of operating a device, the device comprising a processor, a non-volatile memory array, and an accelerator, wherein the accelerator is coupled to the non-volatile memory array bypassing the processor, the method comprising:

• determining a first throughput of the accelerator in a first mode;
• assigning a first portion of the non-volatile memory array to the accelerator according to the first throughput;
• assigning a portion of the non-volatile memory array as a data structure to the first accelerator based on the throughput of the first accelerator;
• operating upon data words of a first width in a first mode, and data words of a second width in a second mode using the first accelerator, wherein the second width is greater than the first width;
• assigning a data structure to the first accelerator in the first mode, wherein the data structure is distributed over a first portion of the of non-volatile memory array;
• assigning a data structure to the first accelerator in the second mode, wherein the data structure is distributed over a second portion of the plurality of non-volatile memory devices;
• and
• wherein the second portion is greater than the first portion.