Memory system and SoC including linear address remapping logic
AssigneeSamsung Electronics Co., Ltd.
InventorDongsik Cho
Life of this patent
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Abstract
A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.
Claims17
A system-on-chip comprising:
- a first memory port;
- a second memory port;
- a memory controller configured to access a first memory device through the first memory port or a second memory device through the second memory port;
- a processor configured to generate memory addresses for accessing a memory region and configured to generate a control signal for selecting a linear mode and a interleave mode, and, when the memory addresses are greater than a base address, the processor generates the control signal such that the linear mode is selected;
- and
- an address remapping logic configured to, in the linear mode, remap the memory addresses into remapped addresses based on the control signal,
- wherein the memory controller is further configured to, in the linear mode, perform a first linear access operation on a first region of the memory region by accessing only the first memory device through the first memory port in response to first remapped addresses of the remapped addresses.
A system-on-chip comprising:
- a first memory port;
- a second memory port;
- an address remapping logic configured to remap memory addresses for accessing a memory region into remapped addresses;
- a processor configured to generate a control signal for selecting the memory addresses when the memory addresses are not greater than a base address and configured to generate a control signal for selecting the remapped addresses when the memory addresses are greater than a base address;
- and
- a memory controller configured to, based on the control signal, perform a partial linear access operation on a first region of a memory region by accessing only a first memory device though the first memory port, and a partial interleave access operation on a second region of the memory region by accessing both the first memory device and a second memory devices through the first and second ports.
A system-on-chip comprising:
- a processor configured to generate memory addresses for accessing a memory region corresponding to first and second memory devices and, when the memory addresses are greater than a base address, configured to generate a control signal to remap the memory addresses into remapped addresses;
- an address remapping logic configured to remap the memory addresses into remapped addresses in response to the control signal;
- and
- a memory controller configured to:
- perform a partial linear access operation on a first region of the memory region in response to the remapped addresses in a partial linear mode, and
- perform a partial interleave access operation on a second region of the memory region in response to the memory addresses, in a partial interleave mode.
Dependencies are inferred from the claim text.