US 12,001,697 B2Granted

Multi-modal refresh of dynamic, random-access memory

AssigneeRambus Inc.

InventorsThomas Vogelsang, Steven C. Woo, Michael Raymond Miller

Life of this patent

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Abstract

A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

Claims19

Dependent claims

An integrated circuit (IC) device comprising:

stacked and bonded memory dies, each memory die having:
a first memory-die request interface to a first set of memory banks;
and
a second memory-die request interface to a second set of memory banks;
wherein each of the first and second sets of memory banks include volatile memory cells;
a controller die bonded to the memory dies, the controller die including:
a first controller to issue first refresh requests to the first memory-die request interfaces of the bonded memory dies;
and
a second controller to issue second refresh requests to the second memory-die request interfaces of the bonded memory dies to issue second refresh requests to the second set of memory banks:
a first refresh-address counter to issue first bank addresses;
and
a first bank-address demultiplexer having:
a first demultiplexer input port coupled to the first refresh-address counter to receive the first bank addresses;
a first demultiplexer output port coupled to the first and second memory-die request interfaces of a first of the memory dies;
and
a second demultiplexer output port coupled to the first memory-die request interfaces of the first of the memory dies and a second of the memory dies.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/503,058Filed 15 Oct 2021 · us provisional application
Priority: 4 Nov 2020
Published: US 2022/0137843 A15 May 2022
Granted: 4 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 3/0634
Configuration or reconfiguration of storage systems: by changing the state or mode of one or more devices
G11C 11/40611
Management or control of the refreshing or charge-regeneration cycles: external triggering or timing of internal or partially internal refresh…
G06F 3/061
Specifically adapted to achieve a particular effect: improving I/O performance
G06F 3/0673
In-line storage system: single storage device

Family

Application63/109,743Us provisional application · filed 4 Nov 2020
US 2022/0137843 A1Pre-grant publication · published 5 May 2022
US 12,001,697 B2This patent

From the US filing history. Foreign family members aren’t listed.

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