Address translation metadata compression in memory devices
AssigneeMicron Technology, Inc.
InventorsBrian Toronyi, Scheheresade Virani
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorsBrian Toronyi, Scheheresade Virani
Estimating the term…
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.
A method comprising:
A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller managing a memory device, cause the controller to:
A system comprising:
Dependencies are inferred from the claim text.