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US 12,001,592 B2Granted
Protecting against resets by untrusted software during cryptographic operations
AssigneeNVIDIA Corporation
InventorsAnuj Rao, Adam Hendrickson, Vaishali Kulkarni, Gobikrishna Dhanuskodi, Naveen Cherukuri
Life of this patent
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Abstract
Apparatuses, systems, and techniques for handling faults by a direct memory access (DMA) engine. When a DMA engine detects an error associated with an encryption or decryption operation, the DMA engine reports the error to a CPU, which may be executing an untrusted software directing a DMA operation, and the secure processor. The DMA engine waits for clearance from the secure processor before responding to further directions from the potentially untrusted software.
Claims20
An accelerator circuit comprising:
- a direct memory access (DMA) engine coupled to a central processing unit (CPU), the DMA engine comprising a cryptographic hardware engine;
- and
- a secure processor coupled to the DMA engine via a private interface and the CPU via an encrypted interface, wherein the DMA engine is to:
- detect an error associated with an encryption or decryption operation by the cryptographic hardware engine;
- set one or more interrupt status bits in a first register accessible by the secure processor;
- report one or more interrupts associated with the error to the CPU and the secure processor;
- receive a reset signal from untrusted software executed by the CPU;
- hold the reset signal until the one or more interrupt status bits are cleared by the secure processor;
- and
- initiate a reset responsive to the one or more interrupt status bits being cleared by the secure processor.
7 more elements
A method comprising:
- detecting, by an accelerator circuit, an error associated with an encryption or decryption operation by a cryptographic hardware engine of a direct memory access (DMA) engine of the accelerator circuit;
- setting one or more interrupt status bits in a register accessible by a secure processor of the accelerator circuit;
- reporting one or more interrupts associated with the error to a central processing unit (CPU) coupled to the accelerator circuit;
- receiving a reset signal from untrusted software executed by the CPU;
- holding the reset signal until the one or more interrupt status bits are cleared by the secure processor;
- and
- initiating a reset responsive to the one or more interrupt status bits being cleared by the secure processor.
4 more elements
A system comprising:
- a central processing unit (CPU);
- and
- a graphics processing unit (GPU) coupled to the CPU, wherein the GPU comprises:
- a direct memory access (DMA) circuit comprising an Advanced Encryption Standard Galois Counter Mode (AES-GCM) hardware engine;
- and
- a processor coupled to the DMA circuit via a private interface and the CPU via an encrypted interface, wherein the DMA circuit is to:
- detect an error associated with an encryption or decryption operation by the AES-GCM hardware engine;
- set one or more interrupt status bits in a first register accessible by the processor;
- report one or more interrupts associated with the error to the CPU;
- receive a reset signal from untrusted software executed by the CPU;
- hold the reset signal until the one or more interrupt status bits are cleared by the processor;
- and
- initiate a reset responsive to the one or more interrupt status bits being cleared by the processor.
10 more elements
Dependencies are inferred from the claim text.