Disabling processor cores for best latency in a multiple core processor

A method, comprising:

• in response to receiving a selection of a number of processor cores to have enabled in a multiple core processor, determining, by a basic input/output system (BIOS) of an information handling system, a different latency for each of a plurality of processor cores in the multiple core processor;
• based on the different latency for each of the processor cores, determining a first subset of the processor cores to enable and a second subset of the processor cores to disable;
• and
• setting, by the BIOS, bits in the model-specific register to indicate that the first subset of the processor cores is enabled and the second subset of the processor cores is disabled, wherein the bits in the model-specific register being set, the method further comprises setting a bit associated with a first processor core to a particular value based on the first processor core having a worst latency for a first integrated memory controller, wherein the particular value of the bit indicates that the first processor core is disabled.

An information handling system, comprising:

• a first dual in-line memory module (DIMM);
• a model-specific register;
• a first processor die of a multiple core processor coupled to the first DIMM, the first processor die including a first plurality of processor cores and a first integrated memory controller to communicate with the first DIMM;
• and
• a basic input/output system to:
• in response to reception of a selection of a number of processor cores to have enabled, calculate a different latency for each of the first processor cores in the first processor die;
• based on the different latency for each of the processor cores, determine a first subset of the first processor cores in the first processor die to enable and a second subset of the first processor cores in the first processor die to disable;
• and
• set bits in the model-specific register to indicate that the first subset of the first processor cores is enabled and the second subset of the first processor cores is disabled, wherein a bit associated with one of the first processor cores is set to a particular value based on the one of the first processor cores having a worst latency for the first integrated memory controller, wherein the particular value of the bit indicates that the one of the first processor cores is disabled.