Processing element array and operating method thereof

A processing element (PE) array comprising:

• a plurality of PEs arranged linearly, wherein a number of the plurality of PEs is N and N is greater than or equal to 3, each of the plurality of PEs comprises a processor and a memory such that the plurality of PEs comprises N processors and N memories, wherein:
• the N memories are configured to store P data, and P is greater than N;
• a first memory to a Nth memory of the N memories are respectively configured to store a first datum to a Nth datum of the P data;
• the Nth memory of the N memories is further configured to store a (N+1)th datum of the P data;
• each of the N processors calculates according to one of the P data stored in one of the N memories corresponding to itself, or calculates according to another one of the P data received from other PE;
• and
• (N+1) transmission circuits, wherein each of the (N+1) transmission circuits is electrically connected to a left PE and a right PE adjacent to each other in the N PEs, each of the (N+1) transmission circuits is configured to receive information from the left PE and sends the information to the right PE, or receive another information from the right PE and sends said another information to the left PE.

A processing element (PE) array comprising:

• M×N PEs arranged in M rows and N columns, wherein both M and N are greater than or equal to 2, each of the M×N PEs comprises a processor, a row memory, and a column memory such that the M×N PEs comprise M×N processors, each of the M rows has N row memories, and each of the N columns has M column memories, wherein:
• the N row memories located in the same row are configured to store P data and P is greater than N;
• a first row memory to a Nth row memory in the N row memories located in the same row are respectively configured to store a first datum to a Nth datum in the P data;
• the Nth row memory in the N row memories located in the same row is configured to store a (N+1)th datum in the P data;
• each of N processors in the same row calculates according to a datum stored in the row memory corresponding to itself, or calculates according to another datum received from other PEs;
• the M column memories located in the same column are configured to store Q data and Q is greater than M;
• a first column memory to a Mth column memory in the M column memories located in the same column are respectively configured to store a first datum to a Mth datum in the Q data;
• the Mth column memory in the N column memories located in the same column is configured to store a (M+1)th datum in the Q data;
• each of M processors in the same column calculates according to a datum stored in the column memory corresponding to itself, or calculates according to another datum received from other PEs;
• (M×N−M) row transmission circuits, wherein:
• each of the (M×N−M) row transmission circuits is electrically connected to a left PE and a right PE adjacent to each other in the N PEs in each of the M rows;
• and
• each of the (M×N−M) row transmission circuits is configured to receive a row data from the left PE and send the row data to the right PE, or receive another row data from the right PE and send said another row data to the left PE;
• and (M×N−N) column transmission circuits, wherein:
• each of the (M×N−N) column transmission circuits is electrically connected to an upper PE and a lower PE adjacent to each other in the M PEs in each of the N columns;
• and
• each of the (M×N−N) column transmission circuits is configured to receive a column data from the upper PE and send the column data to the lower PE, or receive another column data from the lower PE and send said another column data to the upper PE.