Autonomous entry and exit of low latency datapath in PCIe applications
AssigneeAvago Technologies International Sales Pte. Limited
InventorJeffrey Ronald Dorst
Life of this patent
Estimating the term…
Abstract
A PCIe retimer includes read-only vendor registers with low latency mode entry and exit values. In-band low latency switching logic monitors the output of an elastic buffer for read commands of the vendor registers and, when such read commands are received, reads the corresponding address and switches a multiplexer between a link training data path and a low latency data path based on the return value of the read operation. Read commands, and therefore control of data path switching, is handled entirely in-band. Return values of the read operations indicate success or failure of mode switching to the root complex.
Claims20
A PCIe retimer comprising:
- an elastic buffer;
- a link training and status state machine;
- a multiplexer;
- and
- switching logic in data communication with the elastic buffer and the multiplexer, the switching logic comprising:
- a first register configured with a first bit value;
- a second register configured with a second bit value;
- and
- processing logic configured to:
- identify a read signal from the elastic buffer, the read signal configured to instruct the switching logic to read one of the first register or the second register;
- read the register indicated by the read signal;
- and
- apply a signal to the multiplexer corresponding to the first bit value or the second bit value depending on which of the first register or second register was read,
- wherein:
- the first bit value puts the multiplexer in a configuration to utilize the link training and status state machine;
- and
- the second bit value puts the multiplexer in a configuration to bypass the link training and status state machine;
- wherein the PCIe retimer is configured to receive a first signal and boost the first signal by regenerating the first signal as a second signal.
A PCIe device comprising a retimer configured to receive a first signal and boost the first signal by regenerating the first signal as a second signal, the retimer comprising:
- a receiver;
- a transmitter;
- and
- a PCIe retimer comprising:
- an elastic buffer;
- a link training and status state machine;
- a multiplexer;
- and
- switching logic in data communication with the elastic buffer and the multiplexer, the switching logic comprising:
- a first register configured with a first bit value;
- a second register configured with a second bit value;
- and
- processing logic configured to:
- receive a low latency mode entry/exit signal via the receiver;
- populate the elastic buffer with the low latency mode entry/exit signal;
- identify a low latency mode entry/exit signal from the elastic buffer, the low latency mode entry/exit signal configured to instruct the switching logic to read one of the first register or the second register;
- read register indicated by the low latency mode entry/exit signal;
- apply a signal to the multiplexer corresponding to the first bit value or the second bit value based on the low latency mode entry/exit,
- wherein:
- the first bit value puts the multiplexer in a configuration to utilize the link training and status state machine;
- and
- the second bit value puts the multiplexer in a configuration to utilize a low latency data path directly linking the receiver to the transmitter.
A system comprising:
- a first device including a PCIe interface;
- a second device including a PCIe interface;
- and
- a PCIe retimer electronically interposed between the first device and the second device, the PCIe retimer being configured to receive a first signal from the first device and boost the first signal by regenerating the first signal as a second signal, the second signal being output to the second device, the PCIe retimer comprising:
- an elastic buffer;
- a link training and status state machine;
- a multiplexer;
- and
- switching logic in data communication with the elastic buffer and the multiplexer, the switching logic comprising:
- a first register configured with a first bit value;
- a second register configured with a second bit value;
- and
- processing logic configured to:
- identify a read signal from the elastic buffer, the read signal configured to instruct the switching logic to read one of the first register or second vendor address;
- read the register corresponding indicated by the read signal;
- apply a signal to the multiplexer corresponding to the first bit value or the second bit value based on the read signal,
- wherein:
- the first bit value puts the multiplexer in a configuration to utilize the link training and status state machine;
- and
- the second bit value puts the multiplexer in a configuration to bypass the link training and status state machine.
Dependencies are inferred from the claim text.