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US 12,001,351 B2Granted
Multiple-requestor memory access pipeline and arbiter
AssigneeTexas Instruments Incorporated
InventorsAbhijeet Ashok Chachad, David Matthew Thompson
Life of this patent
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Abstract
In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The memory system can include a pipeline for accessing data stored in one of the caches. Requestors can access the data stored in one of the caches by sending requests at a same time that can be arbitrated by the pipeline.
Claims20
A device comprising:
- a set of requestors configured to provide a set of memory transaction requests;
- a first set of arbitration units that includes a respective arbitration unit coupled to each requestor of the set of requestors;
- a cache memory that includes a set of memory banks;
- and
- a pipeline circuit coupled between the first set of arbitration units and the cache memory that includes a set of parallel pipelines that includes a respective pipeline associated with each memory bank of the set of memory banks, wherein:
- each pipeline of the set of parallel pipelines includes a respective arbitration unit of a second set of arbitration units;
- and
- the first set of arbitration units and the second set of arbitration units are coupled to perform, on each memory transaction request of the set of memory transaction requests, a first arbitration using the first set of arbitration units and a second arbitration using the second set of arbitration units.
5 more elements
A device comprising:
- a set of cores;
- a set of level one (L1) caches coupled to the set of cores;
- a set of requestors that includes a set of memory controllers coupled to the set of L1 caches;
- a level two (L2) cache controller coupled to the set of requestors;
- and
- an L2 memory coupled to the L2 cache controller that includes a set of banks, wherein the L2 cache controller includes:
- a first set of arbitration units that includes a respective arbitration unit coupled to each requestor of the set of requestors;
- and
- a pipeline circuit coupled to the first set of arbitration units that includes a set of parallel pipelines that includes a respective pipeline associated with each memory bank of the set of memory banks, wherein each pipeline of the set of parallel pipelines includes a respective arbitration unit of a second set of arbitration units.
6 more elements
A method comprising:
- receiving a set of memory transaction requests from a set of requestors, wherein the set of memory transaction requests are directed to a cache memory that includes a set of memory banks;
- performing, by a first set of arbitration units, a first arbitration on the set of memory transaction requests among subsets of the set of memory transaction requests each associated with a respective requestor of the set of requestors;
- performing, by a second set of arbitration units, a second arbitration on the set of memory transaction requests among subsets of the set of memory transaction requests each associated with a respective memory bank of the set of memory banks;
- and
- thereafter, servicing the set of memory transaction requests using the cache memory.
2 more elements
Dependencies are inferred from the claim text.