Memory access compression using clear code for tile pixels

A method performed by a parallel processor, the method comprising:

• accessing a translation lookaside buffer (TLB) entry for a virtual address;
• and
• determining, based on the TLB entry, a clear status for a virtual page associated with the virtual address, wherein the clear status indicates that the virtual page is a valid page that is cleared to a clear color;
• and
• determining the clear color associated with the virtual page by reading the clear color from a register within the parallel processor.

A data processing system comprising:

• a memory device configured to store a page table that includes a set of page table entries;
• a plurality of processors including a general-purpose graphics processing unit (GPGPU), the GPGPU including:
• a translation lookaside buffer (TLB) to cache a page table entry of the set of page table entries, the page table entry to indicate that a first virtual page is a valid page that is cleared to a clear color;
• and
• circuitry to bypass a memory access for the first virtual page based on the page table entry and determine the clear color for the first virtual page via a read from a register associated with the GPGPU.