Selective distribution of translation entry invalidation requests in a multithreaded data processing system
AssigneeInternational Business Machines Corporation
InventorsDerek E. Williams, Florian Auernhammer
Life of this patent
Estimating the term…
Loading patent…
AssigneeInternational Business Machines Corporation
InventorsDerek E. Williams, Florian Auernhammer
Estimating the term…
A data processing system includes a plurality of processing nodes communicatively coupled to a system fabric. Each of the processing nodes includes a respective plurality of processor cores. Logical partition (LPAR) information for each of a plurality of LPARs is maintained in a register set in each of the processor cores, where the LPAR information indicates, for each of the LPARs, which of the processing nodes may hold an address translation entry for each LPAR. Based on the LPAR information, a first processor core selects a broadcast scope for a multicast request on the system fabric that includes fewer than all of the plurality of processing nodes and issues the multicast request with the selected broadcast scope. The first processor core updates the LPAR information in the register set of a second processor core in another of the plurality of processing nodes via an inter-processor interrupt.
A method of multicast communication in a data processing system including a plurality of processing nodes communicatively coupled to a system fabric for communicating requests, wherein each of the plurality of processing nodes includes a respective plurality of processor cores, the method comprising:
A processing node for a data processing system including a plurality of processing nodes communicatively coupled to a system fabric, the processing unit comprising:
A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
Dependencies are inferred from the claim text.