Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries

A microprocessor, comprising:

• a physically-indexed physically-tagged second-level set-associative cache, wherein each entry of the second-level cache is configured to hold a copy of a line of memory and is uniquely identified by a set index and a way;
• a load queue;
• and
• a load/store unit configured to, during execution of a load instruction that requests load data:
• detect that, based on a load virtual address and a data size specified by the load instruction, a first portion of the load data is to be read from a first line of memory specified by a first load physical memory line address and that a second portion of the load data is to be read from a second line of memory different from the first line of memory and specified by a second load physical memory line address;
• and
• write to an entry of the load queue allocated to the load instruction first and second load physical address proxies (PAPs) for the first and second load physical memory line addresses, respectively, wherein the first load PAP comprises the set index and way that uniquely identifies an entry of the second-level cache that holds a copy of the first line of memory specified by the first load physical memory line address, wherein the second load PAP comprises the set index and way that uniquely identifies an entry of the second-level cache that holds a copy of the second line of memory specified by the second load physical memory line address;
• wherein the entries of the load queue are absent storage for holding the first and second load physical memory line addresses.

A method, comprising:

• in a microprocessor comprising:
• a physically-indexed physically-tagged second-level set-associative cache, wherein each entry of the second-level cache is configured to hold a copy of a line of memory and is uniquely identified by a set index and a way;
• a store queue;
• and
• a load/store unit;
• by the load/store unit, during execution of a store instruction having store data:
• detecting, based on a store virtual address and a data size specified by the store instruction, a first portion of the store data is to be written to a first line of memory specified by a first store physical memory line address and that a second portion of the store data is to be written to a second line of memory different from the first line of memory and specified by a second store physical memory line address;
• writing all the store data to an entry of the store queue allocated to the store instruction;
• and
• writing to the allocated store queue entry first and second store physical address proxies (PAPs) for the first and second store physical memory line addresses, respectively, wherein the first store PAP comprises the set index and way that uniquely identifies an entry of the second-level cache that holds a copy of the first line of memory specified by the first store physical memory line address, wherein the second store PAP comprises the set index and way that uniquely identifies an entry of the second-level cache that holds a copy of the second line of memory specified by the second store physical memory line address;
• wherein the entries of the store queue are absent storage for holding the first and second store physical memory line addresses.

A method, comprising:

• in a microprocessor comprising:
• a physically-indexed physically-tagged second-level set-associative cache, wherein each entry of the second-level cache is configured to hold a copy of a line of memory and is uniquely identified by a set index and a way;
• a load queue;
• and
• a load/store unit;
• by the load/store unit during execution of a load instruction that requests load data:
• detecting that, based on a load virtual address and a data size specified by the load instruction, a first portion of the load data is to be read from a first line of memory specified by a first load physical memory line address and that a second portion of the load data is to be read from a second line of memory different from the first line of memory and specified by a second load physical memory line address;
• and
• writing to an entry of the load queue allocated to the load instruction first and second load physical address proxies (PAPs) for the first and second load physical memory line addresses, respectively, wherein the first load PAP comprises the set index and way that uniquely identifies an entry of the second-level cache that holds a copy of the first line of memory specified by the first load physical memory line address, wherein the second load PAP comprises the set index and way that uniquely identifies an entry of the second-level cache that holds a copy of the second line of memory specified by the second load physical memory line address;
• wherein the entries of the load queue are absent storage for holding the first and second load physical memory line addresses.