Hybrid parallel programming of single-level cell memory

A method comprising:

• causing, by control logic coupled with a page buffer and a set of sub-blocks in a memory array, a first page of single-level cell (SLC) data to be stored in a cache register of the page buffer, wherein the set of sub-blocks comprise memory cells configured as SLC memory;
• causing, by the control logic, the first page of the SLC data to be moved from the cache register to a first data register of multiple data registers of the page buffer;
• causing, by the control logic, a subsequent page of the SLC data to be stored in the cache register;
• causing, by the control logic, the subsequent page and the first page of the SLC data stored in the cache register and in the first data register, respectively, to be concurrently programmed to the set of sub-blocks, wherein the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block of the set of sub-blocks;
• and
• causing, by the control logic, operations for programming the set of sub-blocks to be performed in parallel.

A method comprising:

• causing, by control logic coupled with a page buffer and a set of sub-blocks in a memory array, multiple pages of single-level cell (SLC) data to be sequentially stored within a cache register of the page buffer, wherein the set of sub-blocks comprise memory cells configured as SLC memory;
• causing, by the control logic, the multiple pages to be sequentially moved from the cache register to respective ones of multiple data registers of the page buffer while retaining a final page of the multiple pages in the cache register;
• causing, by the control logic, the multiple pages of the SLC data stored in a combination of the cache register and the multiple data registers to be concurrently programmed to the set of sub-blocks, wherein a respective page of the multiple pages is to be programmed to each respective sub-block of the set of sub-blocks;
• and
• causing, by the control logic, operations for programming the set of sub-blocks to be performed in parallel.