Devices and methods for safe mode of operation in event of memory channel misbehavior

A system-on-a-chip (SoC), comprising:

• a network interface unit (NIU);
• a first memory channel capable of being communicatively connected to the NIU;
• a second memory channel capable of being communicatively connected to the NIU;
• and
• a non-volatile memory configured to store first error information that is read upon booting of the SoC;
• wherein the SoC is configured to:
• obtain the first error information in response to misbehavior in the first memory channel when communicatively connected to the NIU;
• store the first error information in the non-volatile memory;
• reboot the SoC including the first memory channel;
• perform a built-in self-test on the first memory channel during the reboot;
• generate second error information and write the second error information over the first error information in the non-volatile memory in response to the built-in-self-test indicating no misbehavior in the first memory channel during the reboot;
• configure the first memory channel to be communicatively disconnected from the NIU and configure the second memory channel to be communicatively connected to the NIU in response to reading the first error information in the non-volatile memory during the reboot;
• and
• reboot the SoC including the first memory channel and the second memory channel in response to no misbehavior in the first memory channel.

A non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a processor to reconfigure memory channel routing within a system-on-a-chip (SoC) to perform operations comprising:

• obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC;
• storing the first error information in non-volatile memory that is read upon booting of the SoC;
• rebooting the SoC including the first memory channel;
• performing a built-in self-test on the first memory channel during the reboot;
• generating second error information and writing the second error information over the first error information in the non-volatile memory in response to the built-in-self-test indicating no misbehavior in the first memory channel during the reboot;
• configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the first error information in the non-volatile memory during the reboot;
• and
• rebooting the SoC including the first memory channel and the second memory channel in response to no misbehavior in the first memory channel.