Memory device with dynamic processing level calibration
AssigneeMicron Technology, Inc.
InventorsLarry J. Koudele, Bruce A. Liikanen
Life of this patent
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Abstract
A system includes a memory array; and a processing device coupled to the memory array. The processing device may be configured to iteratively adjust an active processing level, wherein, for each iteration, the processing device is configured to: determine a first set of read results corresponding to the active processing level, determine a second set of read results based on an offset processing level different than the active processing level, and incrementally adjust the active processing level based on a comparison of the first and the second read results.
Claims20
A system, comprising:
- a memory array;
- and
- a processing device coupled to the memory array, the processing device configured to iteratively adjust an active processing level used to process data stored in the memory array, wherein, for each iteration, the controller is configured to:
- determine a first set of read results based on the active processing level,
- determine a second set of read results based on using an offset processing level different than the active processing level, and
- incrementally adjust the active processing level based on a comparison of the first and the second sets of read results.
A method of operating a system including a processing device and a memory array, the method comprising iteratively:
- determining a first set of read results based on using an active processing level;
- determining a second set of read results based on using an offset processing level;
- and
- incrementally adjust the active processing level based on a comparison of the first set of read results and the second set of read results for each iteration.
A system, comprising:
- a memory array including non-volatile memory cells arranged in memory pages;
- and
- a processing device coupled to the memory array, the processing device configured to iteratively adjust a current read level voltage, wherein, for each iteration, the processing device is configured to:
- determine a first set of read results corresponding to the active read level voltage,
- determine a second set of read results based on using an offset read level voltage different from the active read level voltage, and
- incrementally increase or decrease the active read level voltage for the memory page based on a comparison of the first and second sets of read results.
Dependencies are inferred from the claim text.