Deferred error code correction with improved effective data bandwidth performance
AssigneeMicron Technology, Inc.
InventorGil Golov
Life of this patent
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Abstract
A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.
Claims20
A method comprising:
- starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition, wherein, during the deferred period of operation, an error code correction (ECC) portion of a memory bank is not accessed during operations;
- issuing a command to read data from or write data to the memory bank of the memory system in response to an operation received from a processor during the deferred period of operation;
- generating ECC data prior to receiving a response to the command from the memory bank during the deferred period of operation;
- caching the ECC data in a local cache;
- and
- returning a result of the command to the processor while the ECC data is present in the local cache.
A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor, the computer program instructions defining steps of:
- starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition, wherein, during the deferred period of operation, an error code correction (ECC) portion of a memory bank is not accessed during operations;
- issuing a command to read data from or write data to the memory bank of the memory system in response to an operation received from a processor during the deferred period of operation;
- generating ECC data prior to receiving a response to the command from the memory bank during the deferred period of operation;
- caching the ECC data in a local cache;
- and
- returning a result of the command to the processor while the ECC data is present in the local cache.
A memory system comprising:
- a plurality of memory banks;
- a bus connected to the memory banks;
- and
- a controller connected to the bus, the controller configured to perform operations of:
- starting a deferred period of operation of a memory system in response to detecting a satisfaction of a condition, wherein, during the deferred period of operation, an error code correction (ECC) portion of a memory bank is not accessed during operations;
- issuing a command to read data from or write data to the memory bank of the memory system in response to an operation received from a processor during the deferred period of operation;
- generating ECC data prior to receiving a response to the command from the memory bank during the deferred period of operation;
- caching the ECC data in a local cache;
- and
- returning a result of the command to the processor while the ECC data is present in the local cache.
Dependencies are inferred from the claim text.