Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

A system comprising:

• a memory;
• a first die having a ferroelectric logic or a paraelectric logic;
• a second die having CMOS based logic, wherein the second die is coupled to the first die in a 2.5D configuration or a 3D configuration, wherein the memory is coupled to the first die and/or the second die;
• a power management unit including circuitry which is coupled to the first die and the second die, wherein the circuitry is to manage power of the first die and the second die based on a first throughput ratio of the ferroelectric logic or the paraelectric logic and a second throughput ratio of the CMOS based logic,
• wherein the ferroelectric logic or the paraelectric logic includes at least three capacitors with first terminals to receive inputs and second terminals that are directly coupled to a node, wherein at least one capacitor of the at least three capacitors includes non-linear polar material, wherein the ferroelectric logic or the paraelectric logic includes a reset mechanism coupled to the node, wherein the reset mechanism is operable to reset charge on the node in a reset phase separate from an evaluation phase of the inputs, wherein the first die and the second die have an overlapping functionality, wherein the power management unit is operable to manage power of the overlapping functionality in the first die and the second die;
• and
• a communication interface to allow the first die or the second die to communicate with another device.

A non-transitory machine-readable storage media having machine-readable instructions stored that when executed cause of one or more machines to perform a method, the method comprising:

• computing a first throughput ratio of a ferroelectric logic or a paraelectric logic, wherein the ferroelectric logic or the paraelectric logic includes at least three capacitors with first terminals to receive inputs and second terminals that are directly coupled to a node, wherein at least one capacitor of the at least three capacitors includes non-linear polar material, wherein the ferroelectric logic or the paraelectric logic includes a reset mechanism coupled to the node, wherein the reset mechanism is operable to reset charge on the node in a reset phase separate from an evaluation phase of the inputs;
• computing a second throughput ratio of a CMOS based logic;
• and
• managing power of the ferroelectric logic or the paraelectric logic and the CMOS based logic based on the first throughput ratio and the second throughput ratio, wherein the CMOS based logic and the ferroelectric logic or the paraelectric logic have an overlapping functionality, wherein a power management unit is operable to manage power of the overlapping functionality in the CMOS based logic and the ferroelectric logic or the paraelectric logic.