Device and method for reducing save-restore latency using address linearization

A method of transitioning between power states of a device comprising:

• executing a program using data stored in configuration registers;
• for a first reduced power state, saving data of a first portion of configuration registers to memory using a set of addresses of a first linear address space;
• and
• for a second reduced power state:
• saving data of a second portion of the configuration registers to the memory using a set of addresses of a second linear address space separate from the first linear address space;
• and
• saving data of a third portion of the configuration registers to the memory using a set of addresses of a third linear address space separate from the first linear address space and the second linear address space,
• wherein the configuration registers are assigned to a component of the device.

A non-transitory computer readable medium comprising instructions for causing a computer to execute a method of transitioning between power states of a device, the instructions comprising:

• executing a program using data stored in configuration registers;
• for a first reduced power state, saving data of a first portion of configuration registers to memory using a set of addresses of a first linear address space;
• and
• for a second reduced power state:
• saving data of a second portion of the configuration registers to the memory using a set of addresses of a second linear address space separate from the first linear address space;
• and
• saving data of a third portion of the configuration registers to the memory using a set of addresses of a third linear address space separate from the first linear address space and the second linear address space,
• wherein the configuration registers are assigned to a component of the device.