Controlling a processor clock

A computer system comprising:

• a first clock generator configured to generate a f irst clock signal at a first clock signal frequency at a first time and at a reduced first clock signal frequency at a second time;
• a second clock generator configured to generate a second clock signal which has a frequency lower than the first clock signal frequency of the first clock signal;
• switching circuitry configured to provide one of the first clock signal or the second clock signal to a processor, wherein the switching circuitry is configured to provide the first clock signal to the processor at the first time and at the second time;
• monitoring circuitry configured to detect a threshold event indicating that an application running on the processor has exceeded a power budget;
• and
• controlling circuitry configured to, responsive to detection of the threshold event, cause the first clock generator to generate the reduced first clock signal frequency by reducing a frequency of the first clock signal from the first clock signal frequency and to cause the switching circuitry to provide the second clock signal to the processor while the frequency of the first clock signal is being reduced.