Balancing current consumption between different voltage sources

A system comprising:

• a first voltage source to supply power to core memory circuitry of a memory device;
• a voltage regulator coupled with the first voltage source;
• a first transistor coupled between an output of the voltage regulator and input/output (I/O) circuitry;
• a second voltage source to supply power to a set of I/O buffers of the memory device, the first voltage source providing a higher voltage than that of the second voltage source;
• a second transistor coupled between the second voltage source and the I/O circuitry;
• and
• control logic coupled with gates of the first transistor and the second transistor, the control logic to perform operations comprising:
• causing the second transistor to be activated to permit current to flow from the second voltage source to the I/O circuitry;
• in response to detecting a current draw from the I/O circuitry that satisfies a first threshold criterion, causing the first transistor to be activated;
• and
• causing the second transistor to be deactivated over a time interval during which the I/O circuitry is powered by the first voltage source and the second voltage source.

A method comprising:

• causing, using a first voltage source, core memory circuitry of a memory device to be powered;
• causing, using a second voltage source, a set of input/output (I/O) buffers of the memory device to be powered;
• causing, by control logic of the memory device, upon startup of the memory device, a first transistor to be activated, the first transistor coupled between the second voltage source and I/O circuitry of the memory device;
• causing, by the control logic, in response to detecting a current draw from the I/O circuitry that satisfies a first threshold criterion, a second transistor to be activated, the second transistor coupled between a voltage regulator of the first voltage source and the I/O circuitry;
• and
• causing, by the control logic, the first transistor to be deactivated over a time interval during which the I/O circuitry is powered by the first voltage source and the second voltage source.