Barriers and synchronization for machine learning at autonomous machines

A data processing system comprising:

• a memory device;
• and
• a graphics processor coupled with the memory device, the graphics processor including:
• a first processing resource;
• a second processing resource coupled with the first processing resource, wherein the first processing resource and the second processing resource each include a separate respective local memory and instruction execution resources configured to concurrently execute a plurality of threads;
• a shared memory coupled with the first processing resource and the second processing resource, wherein the shared memory is accessible to the first processing resource and the second processing resource;
• and
• scheduler hardware including first circuitry configured to:
• receive a thread group for scheduling, wherein the thread group includes program code configured to store data within the local memory and is programmed for execution on a single processing resource;
• based on a hint associated with the thread group, map the local memory to the shared memory;
• and
• schedule threads of the thread group for execution via multiple processing resources including the first processing resource and the second processing resource, wherein the program code of the thread group that is configured to store data within the local memory is to store the data within the shared memory;
• second circuitry to:
• determine that the thread group is associated with a hint;
• evaluate a memory access performance impact of mapping the local memory to the shared memory based on an amount of shared memory accessed by the program code of the thread group;
• and
• based on the evaluation, provide the hint to the first circuitry;
• and
• wherein the first processing resource and the second processing resource are to execute scheduled threads of the thread group via respective instruction execution resources.

A method comprising:

• receiving a thread group for scheduling to multiple processing resources each including a respective local memory and instruction execution resources configured to concurrently execute a plurality of threads;
• determining that the thread group is associated with a hint;
• evaluating, at second circuitry, a memory access performance impact of mapping respective local memories of the multiple processing resources to a shared memory based on an amount of shared memory to be accessed by program code of the thread group due to the mapping;
• providing the hint to first circuitry based on the evaluation;
• mapping, at the first circuitry, the respective local memories of the multiple processing resources to the shared memory based on the hint provided by the second circuitry;
• scheduling threads of the thread group for execution to the multiple processing resources, wherein the thread group is associated with program code that is configured to store data within respective local memories of the multiple processing resources;
• executing the thread group via the multiple processing resources, wherein, within a processing resource of the multiple processing resources, and based on the mapping, the program code associated with the thread group is to store the data within the shared memory instead of the respective local memories of the multiple processing resources.