Array substrate and liquid crystal display panel
AssigneeWuhan China Star Optoelectronics Technology Co., Ltd.
InventorLifang Wang
Life of this patent
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Abstract
An array substrate and a liquid crystal display panel are provided. By arranging scan lines on a second metal layer in the array substrate, a width of a channel of a thin-film transistor is not related to a width of a scan line, so that the width of the scan line can be increased to reduce resistance of the scan line. In addition, the impedance of the second metal layer is relatively small, so that the impedance of the scan line can be reduced. Furthermore, a channel width of the thin-film transistor is relatively small, which improves charging efficiency of the array substrate and reduces the distortion difference of scan signals.
Claims20
An array substrate, comprising:
- a substrate;
- an active layer disposed on a side of the substrate;
- a gate insulating layer disposed on a side of the active layer away from the substrate;
- a first metal layer disposed on the side of the active layer away from the substrate and formed into a gate electrode disposed;
- an interlayer dielectric layer disposed on a side of the first metal layer away from the gate insulating layer;
- and
- a second metal layer disposed on a side of the interlayer dielectric layer away from the first metal layer and comprising a source electrode, a drain electrode, and a scan line;
- wherein the array substrate further comprises a data line comprising a first part included in the first metal layer and a second part included in the second metal layer, wherein at a junction of the scan line and the data line, the second part of the data line is connected to the first part of the data line through the interlayer dielectric layer, and the scan line is connected to the gate electrode through the interlayer dielectric layer.
A liquid crystal display panel, comprising an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the array substrate comprises:
- a substrate;
- an active layer disposed on a side of the substrate;
- a gate insulating layer disposed on a side of the active layer away from the substrate;
- a first metal layer disposed on the side of the active layer away from the substrate and formed into a gate electrode;
- an interlayer dielectric layer disposed on a side of the first metal layer away from the gate insulating layer;
- and
- a second metal layer disposed on a side of the interlayer dielectric layer away from the first metal layer and comprising a source electrode, a drain electrode, and a scan line;
- wherein the array substrate further comprises a data line comprising a first part included in the first metal layer and a second part included in the second metal layer, wherein at a junction of the scan line and the data line, the second part of the data line is connected to the first part of the data line through the interlayer dielectric layer, and the scan line is connected to the gate electrode through the interlayer dielectric layer.
Dependencies are inferred from the claim text.