Modular sequencer for radar applications

A method, comprising:

• reading a program from a memory of a radar device,
• wherein the radar device comprises:
• the memory,
• a global timer to maintain a cycle count of digital clock cycles,
• a set of radar components that are used in at least one of a transmit channel of the radar device for transmitting radar signals or a receive channel for receiving radar signals,
• a decoder, and
• a set of first-in first-out (FIFO) buffers, wherein each FIFO buffer of the set of FIFO buffers is associated with a respective radar component of the set of radar components;
• decoding, by the decoder, the program;
• generating, based at least in part on the program and for each radar component of the set of radar components, a control value and a timestamp associated with the control value,
• wherein the control value is a value to be provided as an input to the respective radar component in accordance with a changing configuration during operation of the radar device at a time indicated by the timestamp, and
• wherein the timestamp indicates a cycle count;
• storing, by each FIFO buffer, at least the control value and the timestamp of the respective radar component;
• and
• providing, by each FIFO buffer, the control value as the input to the respective radar component at the time indicated by the timestamp.

A system, comprising:

• a decoder to:
• read, from a memory, a program associated with controlling radar operation of a set of components of the system, wherein the set of components are used in at least one of a transmit channel of the system for transmitting signals or a receive channel of the system for receiving signals,
• decode the program to generate for each component of the set of components a control value and a timestamp associated with the control value based at least in part on the program,
• wherein the control value is a value to be provided to a respective component of the set of components in accordance with a changing configuration during operation of the system at a time indicated by the timestamp,
• wherein the timestamp indicates a cycle count of a global timer configured to maintain a cycle count of digital clock cycles that is associated with a start of the frequency ramp or an end of the frequency ramp;
• and
• a set of first-in first-out (FIFO) buffers, wherein each FIFO buffer is configured to:
• store at least the control value and the timestamp of the respective component of the system, and
• provide the control value to the respective component at the time indicated by the timestamp.