Device under test (DUT) measurement circuit having harmonic minimization

A system comprising:

• a measurement circuit including:
• a driver circuit having a clock input, a first frequency control input, and a driver output, the driver output coupled to a device under test (DUT) terminal;
• a DUT parameter circuit having a processing input, a second frequency control input, and a DUT parameter output, the processing input coupled to the DUT terminal;
• and
• a control circuit having a first frequency control output and a second frequency control output, the first frequency control output coupled to the first frequency control input, and the second frequency control output coupled to the second frequency control input.

A method for device under test (DUT) management, the method comprising:

• providing, by a DUT management circuit, an excitation signal having a target frequency;
• controlling, by the DUT management circuit, sampling control parameters based on harmonics at the target frequency;
• obtaining, by the DUT management circuit, sense signal samples from sense signals related to the DUT responsive to the sampling control parameters and the excitation signal;
• estimating, by the DUT management circuit, a parameter based on the sense signal samples;
• and
• performing, by the DUT management circuit, DUT management operations based on the estimated parameter.