Integrated circuit including test circuit and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsChangho Han, Mijeong Lim, Yuncheol Kim, Kwanghun Oh
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Abstract
An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.
Claims18
An integrated circuit comprising:
- first to nth metal layers vertically stacked on a substrate;
- and
- a test circuit configured to output a test result signal according to a characteristic of each of the first to nth metal layers,
- wherein the test circuit comprises:
- first to nth test circuits configured to generate a plurality of clock signals, each clock signal of the plurality of clock signals having a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and
- wherein n is a natural number,
- wherein each of the first to nth test circuits comprises a first ring oscillator and a second ring oscillator,
- wherein a frequency of a first clock signal output from the first ring oscillator and a frequency of a second clock signal output from the second ring oscillator are different from each other,
- wherein the first ring oscillator comprises a plurality of inverters connected with each other using a first test pattern formed in a corresponding metal layer of the first to nth metal layers,
- wherein the second ring oscillator comprises a plurality of inverters connected with each other using a second test pattern formed in the corresponding metal layer of the first to nth metal layers, and
- wherein an extension length of the first test pattern and an extension length of the second test pattern are different from each other.
An integrated circuit comprising a test circuit,
- wherein the test circuit comprises:
- a first ring oscillator comprising a plurality of inverters connected with each other using a first test pattern formed in a first metal layer among a plurality of metal layers that are vertically stacked on each other;
- and
- a second ring oscillator comprising a plurality of inverters connected with each other using a second test pattern formed in the first metal layer,
- wherein an extension length of the first test pattern of the first metal layer and an extension length of the second test pattern of the first metal layer are different from each other.
A method of manufacturing an integrated circuit comprising a plurality of metal layers, the method comprising:
- obtaining frequencies of test result signals from a plurality of ring oscillators in a plurality of test circuits, wherein each test circuit includes at least two ring oscillators having test patterns formed in a specific metal layer among the plurality of metal layers, and wherein the test patterns are different in extension lengths thereof;
- and
- extracting a resistance value and a capacitance value of a pattern formed in the specific metal layer by performing machine learning on the frequencies of the test result signals.
Dependencies are inferred from the claim text.