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US 11,999,162 B2Granted
Fluid ejection devices including a first memory and a second memory
AssigneeHewlett-Packard Development Company, L.P.
InventorBoon Bing Ng
Life of this patent
Estimating the term…
Abstract
An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first data lines, a second data line, a first memory element, and a second memory element. The first memory element is enabled in response to first data on the plurality of first data lines. The second memory element is enabled in response to second data on the second data line.
Claims16
An integrated circuit comprising:
- a plurality of first data lines;
- a second data line;
- an ID line;
- a first select line;
- a second select line;
- a first latch having an input coupled with the ID line;
- a second latch having an input coupled with the ID line and an output coupled with a plurality of transistors, wherein a gate of a first transistor of the plurality of transistors is coupled with the output of the second latch and wherein a gate of a second transistor of the plurality of transistors is coupled with the second data line;
- a first memory element to be enabled in response to first data on the plurality of first data lines and in response to a first logic level on the first select line;
- and
- a second memory element to be enabled in response to second data on the second data line and in response to a first logic level on the second select line and a first logic level on the ID line, wherein the second latch turns off the first transistor of the plurality of transistors to access, responsive to the first logic level on the ID line, the second memory element.
7 more elements
A method for accessing a first memory element and a second memory element of an integrated circuit, the method comprising:
- generating a first signal via a first latch having an input coupled with an ID line;
- generating, sequentially with the first signal, a second signal via a second latch having an input coupled with the ID line and an output coupled with a plurality of transistors, wherein a gate of a first transistor of the plurality of transistors is coupled with the output of the second latch and wherein a gate of a second transistor of the plurality of transistors is coupled with the second data line;
- enabling the first memory element in response to a first select signal and first data on a plurality of first data lines;
- and
- enabling the second memory element in response to a second select signal and second data on a second data line, wherein the second latch turns off the first transistor of the plurality of transistors to access, responsive to the first logic level on the ID line, the second memory element.
2 more elements
Dependencies are inferred from the claim text.