Signal transmission circuit and method, and integrated circuit (IC)

An integrated circuit (IC) testing method, configured for a signal transmission circuit, comprising:

• outputting, by an input circuit, a first test signal to an input port of a first stage of transfer circuit in a transfer chain in response to a first control signal and a clock signal, wherein the transfer chain comprises multiple stages of serially-connected transfer circuits, adjacent two stages of transfer circuits in the transfer chain are connected via a through silicon via (TSV) therebetween, and the first stage of transfer circuit is a transfer circuit on one end of the transfer chain connected to the input circuit;
• sequentially transmitting, by the multiple stages of transfer circuits, the first test signal along the transfer chain in response to the clock signal;
• when the first test signal is transmitted to an output port of a stage of transfer circuit, outputting, by a signal output port connected to an input port of the transfer circuit, the first test signal to a chip layer of the IC;
• and
• transmitting, by a mode selection circuit, the first test signal to the input port of the stage of transfer circuit under a control of the first control signal, or transmitting, by the mode selection circuit, a second test signal to the output port of the stage of transfer circuit under the control of the first control signal, wherein the second test signal is connected to each signal output port, the first test signal and the second test signal are transmitted to an adjacent chip layer via a same TSV, and the mode selection circuit comprises:
• a first input port connected to the first test signal;
• a second input port connected to the second test signal;
• a control port connected to the first control signal;
• a first output port connected to the input port of the stage of transfer circuit and configured to transmit the first test signal, and
• a second output port connected to an output port of the stage of transfer circuit and configured to transmit the second test signal.

An integrated circuit (IC), comprising a signal transmission circuit, wherein the signal transmission circuit comprises:

• an input circuit, configured to generate a first test signal in response to a first control signal and a clock signal;
• a transfer chain, comprising multiple stages of serially-connected transfer circuits, wherein adjacent two stages of transfer circuits in the transfer chain are connected via a through silicon via (TSV) therebetween, a transfer circuit on one end of the transfer chain is connected to the input circuit, and the multiple stages of transfer circuits transfer the first test signal stage by stage in response to the clock signal;
• multiple signal output ports, wherein a first test signal input port of each stage of transfer circuit is correspondingly connected to one of the multiple signal output ports coupled to one of chip layers of the IC;
• and
• a mode selection circuit comprising:
• a first input port connected to the first test signal;
• a second input port connected to a second test signal;
• a control port connected to the first control signal;
• a first output port connected to the input port of the stage of transfer circuit and configured to transmit the first test signal to the input port of the stage of transfer circuit under a control of the first control signal;
• and
• a second output port connected to an output port of the stage of transfer circuit and configured to transmit the second test signal to the output port of the stage of transfer circuit under the control of the first control signal,
• wherein the first test signal and the second test signal are transmitted to an adjacent chip layer via a same TSV, and the second test signal is connected to the multiple signal output ports.