US 11,962,303 B1Granted

High-performance flip-flops having low clock load and embedded level shifting

AssigneeSteve Dao

InventorSteve Dao

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Abstract

An architecture for high-performance flip-flops having minimal clock-activated transistors is disclosed. The flip-flops operating in a first voltage domain can receive an input signal from a second voltage domain. The flip-flops include a first latch electrically coupled to a second latch. The first latch includes a first output and a second output. The second latch further includes a first and a second keeper pull-up sub-circuit which electrically couples to the first and second output of the first latch. The clock-gating functionality of the first and second keeper pull-up sub-circuits is merged with the first latch to reduce the loading on the clock signal, and thus the operation of the flip-flop is contention-free and fully-static. An embodiment of the second latch includes only one clock-activated transistor for low-power application. Another embodiment includes two clock-activated transistors for high-speed application. The high-performance flip-flops have near-zero setup time and a two-stage propagation delay.

Claims19

Dependent claims

A flip-flop circuit, comprising:

a first latch operating in a first voltage domain, wherein the first latch comprises:
four clock-activated transistors comprising at least a first clock-activated transistor and a second clock-activated transistor;
a first output node;
and
a second output node;
a second latch operating in the first voltage domain, wherein the second latch comprises:
a first keeper pull-up sub-circuit coupled to the first output node,
wherein the first keeper pull-up sub-circuit is electrically coupled to the first-clock-activated transistor of the first latch and the first clock-activated transistor is a clock-gated device for the first keeper pull-up sub-circuit;
a second keeper pull-up sub-circuit coupled to the second output node,
wherein the second keeper pull-up sub-circuit is electrically coupled to the second clock-activated transistor of the first latch and the second clock-activated transistor is a clock-gated device for the second keeper pull-up sub-circuit;
a first pull-down network;
and
a second pull-down network,
wherein the second latch is configured to merge pull-up functionality of the first keeper pull-up sub-circuit with the first clock-activated transistor of the first latch and to merge pull-up functionality of the second keeper pull-up sub-circuit with the second clock-activated transistor of the first latch.

11 more elements

Dependencies are inferred from the claim text.