Semiconductor device
AssigneeNuvoton Technology Corporation Japan
InventorsKazuyuki Nakanishi, Akio Hirata
Life of this patent
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Abstract
A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.
Claims12
A semiconductor device comprising:
- a plurality of line layers;
- a first line;
- and
- a second line that is not connected to the first line and is provided to transfer a signal having a level same as a level of a signal transferred through the first line,
- wherein the first line and the second line are included in different layers out of the plurality of line layers, and
- a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers and
- the first line and the second line are included in a dual interlocked storage cell (DICE) latch circuit.
A semiconductor device comprising:
- a plurality of line layers;
- a first line;
- and
- a second line that is not connected to the first line and is provided to transfer a signal having a level same as a level of a signal transferred through the first line, wherein:
- the first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers, and
- wherein the first line and the second line are included in a built-in soft error resiliency (BISER) flip-flop circuit.
Dependencies are inferred from the claim text.