Unsuccessful write retry buffer
AssigneeRambus Inc.
InventorsHongzhong Zheng, Brent Haukness
Life of this patent
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Abstract
A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.
Claims20
A module, comprising:
- a first memory device disposed on the module and including a first write retry buffer, the first memory device to, based on a first verify operation performed by the first memory device determining a first attempted write failed in a manner that causes loss of data, store a first entry in the first write retry buffer, the first memory device to also output a first indicator that indicates whether the first write retry buffer meets a threshold criteria associated with an amount of unused entries in the first write retry buffer;
- a second memory device disposed on the module and including a second write retry buffer, the second memory device to, based on a second verify operation performed by the second memory device determining a second attempted write failed in a manner that causes loss of data, store a second entry in the second write retry buffer;
- and
- a first interface to receive a command from a memory controller, the first memory device to, in response to the command, retry the first attempted write using the first entry, the second memory device to, in response to the command, retry the second attempted write using the second entry.
A method of operating a memory module, comprising:
- in response to a first verify operation performed by a first memory device determining a first attempted write failed in a manner that causes loss of data, storing, in a first internal write retry buffer of the first memory device, a first entry;
- in response to a second verify operation performed by a second memory device determining a second attempted write failed in a manner that causes loss of data, storing, in a second internal write retry buffer of the second memory device, a second entry;
- in response to a command from a memory controller, retrying, by the first memory device, the first attempted write using the first entry;
- in response to the command from the memory controller, retrying, by the second memory device, the second attempted write using the second entry;
- and
- outputting, by the first memory device, a first indicator that indicates whether the first internal write retry buffer meets a threshold criteria associated with an amount of unused entries in the first internal write retry buffer.
A memory controller, comprising:
- a first interface to communicate a first write operation to a first memory device, the first interface to communicate a second write operation to the first memory device, the first memory device to perform a first verify operation after the first write operation is attempted, the first memory device to store a first entry in a first internal write retry buffer in response to the first verify operation determining the first write operation failed in a manner that causes loss of data;
- a second interface to receive an indicator that at least one of the first internal write retry buffer meets a threshold criteria associated with a number of unused entries left in the first internal write retry buffer;
- and
- a scheduler to, in response to the indicator, schedule a first command to be sent to the first memory device, the first command to cause the first memory device to retry the first write operation.
Dependencies are inferred from the claim text.