Input clock buffer and clock signal buffereing method
AssigneeElite Semiconductor Microelectronics Technology Inc.
InventorShu-Han Nien
Life of this patent
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Abstract
An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.
Claims16
An input clock buffer, comprising:
- a first capacitor;
- a second capacitor;
- a first amplifier, configured to generate a first output signal, comprising a first input terminal coupled to the first capacitor and comprising a second input terminal coupled to the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal and form a first pair of signal paths for the differential input signal;
- a second amplifier, configured to generate a second output signal, comprising a first input terminal and a second input terminal, wherein the first input terminal of the second amplifier and the second input terminal of the second amplifier form a second pair of signal paths for the differential input signal;
- a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal;
- and
- a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.
A clock signal buffering method, comprising:
- (a) filtering a DC component of a differential input signal;
- (b) forming a first pair of signal paths for the differential input signal by input terminals of a first amplifier after filtering the DC component;
- (c) generating a first output signal by the first amplifier;
- (d) forming a second pair of signal paths for the differential input signal by input terminals of a second amplifier;
- (e) generating a second output signal by the second amplifier;
- (f) generating a frequency detection signal according to a frequency of the differential input signal;
- and
- (g) selectively coupling an output of the first amplifier and an output of the second amplifier according to the frequency detection signal.
Dependencies are inferred from the claim text.