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US 11,910,643 B1Granted
Low cost micro OLED structure and method
AssigneeMeta Platforms Technologies, LLC
InventorsMin Hyuk Choi, Cheonhong Kim, Zhiming Zhuang
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a display system includes forming a display element having a display active area over a silicon backplane, forming a display driver integrated circuit (DDIC), and bonding the display element to the display driver integrated circuit (DDIC). The display active area may include a light emitting diode such as an organic light emitting diode (OLED). Separately forming the display and the display circuitry may simplify formation of the OLED and allow for a higher density control interface between the display and the DDIC.
Claims20
A display system comprising:
- a display element including a display active area disposed over a semiconductor backplane, wherein the display active area comprises a plurality of nodes above a minimum node size formed according to a first process node including a gate driver and a source driver integrated into the semiconductor backplane;
- a discrete display driver integrated circuit (DDIC) that includes a display package with one or more control circuit elements, wherein the control circuit elements in the display package of the DDIC are formed separately from the semiconductor backplane, — and include a display serial interface configured to provide packet-based video data to the display element, as well as a timing controller configured to receive the packet-based video data, format the video data for input by the source driver, and generate control signals for the gate and source drivers, and wherein the DDIC comprises a plurality of nodes below a maximum node size that were formed according to a second, different process node;
- and
- an interconnection component disposed between the display element and the discrete DDIC, wherein the interconnection component communicatively links the control circuit elements in the display package of the DDIC to the display element.
1 more element
An apparatus comprising:
- a display element including a display active area disposed over a semiconductor backplane, wherein the display active area comprises a plurality of nodes above a minimum node size formed according to a first process node including a gate driver and a source driver integrated into the semiconductor backplane;
- a discrete display driver integrated circuit (DDIC) that includes a display package with one or more control circuit elements, wherein the control circuit elements in the display package of the DDIC are formed separately from the semiconductor backplane and include a display serial interface configured to provide packet-based video data to the display element, as well as a timing controller configured to receive the packet-based video data, format the video data for input by the source driver, and generate control signals for the gate and source drivers, and wherein the DDIC comprises a plurality of nodes below a maximum node size that were formed according to a second, different process node;
- and
- an interconnection component disposed between the display element and the discrete DDIC, wherein the interconnection component communicatively links the control circuit elements in the display package of the DDIC to the display element.
1 more element
A method of manufacturing comprising:
- providing a display element including a display active area disposed over a semiconductor backplane, wherein the display active area comprises a plurality of nodes above a minimum node size formed according to a first process node including a gate driver and a source driver integrated into the semiconductor backplane;
- providing a discrete display driver integrated circuit (DDIC) that includes a display package with one or more control circuit elements, wherein the control circuit elements in the display package of the DDIC are formed separately from the semiconductor backplane and include a display serial interface configured to provide packet-based video data to the display element, as well as a timing controller configured to receive the packet-based video data, format the video data for input by the source driver, and generate control signals for the gate and source drivers, and wherein the DDIC comprises a plurality of nodes below a maximum node size that were formed according to a second, different process node;
- and
- providing an interconnection component disposed between the display element and the discrete DDIC, wherein the interconnection component communicatively links the control circuit elements in the display package of the DDIC to the display element.
1 more element
Dependencies are inferred from the claim text.