Memory device and manufacturing method thereof

A method for manufacturing a memory device comprising:

• forming a bottom conductive line over a substrate;
• after forming the bottom conductive line over the substrate, forming a dielectric layer over the bottom conductive line and the substrate, wherein the dielectric layer is in direct contact with a sidewall of the bottom conductive line;
• forming a bottom electrode via opening in the dielectric layer to expose an inner sidewall of the dielectric layer and the bottom conductive line;
• forming a selector in the bottom electrode via opening, in direct contact with the inner sidewall of the dielectric layer, and over the bottom conductive line, wherein after forming the selector in the bottom electrode via opening, the dielectric layer is a single piece of continuous material and in direct contact with both the selector and the sidewall of the bottom conductive line;
• forming a memory layer over the selector such that a bottommost portion of the memory layer is above a top surface of the dielectric layer;
• and
• forming a top conductive line over the memory layer.

A method for manufacturing a memory device comprising:

• forming a bottom electrode in a bottom electrode via opening in a first dielectric layer;
• forming a selector above the bottom electrode and in the first dielectric layer, wherein a maximum width of the selector is substantially equal to a maximum width of the bottom electrode;
• forming a capping layer above the selector and in the first dielectric layer, wherein a sidewall of the bottom electrode, a sidewall of the selector, and a sidewall of the capping layer are coplanar, wherein forming the capping layer comprises:
• depositing a capping material in the bottom electrode via opening and over the first dielectric layer;
• and
• planarizing the capping material with a top surface of the first dielectric layer to form the capping layer in the bottom electrode via opening;
• forming a memory material layer above and in direct contact with the planarized capping layer and the first dielectric layer;
• etching the memory material layer to form a memory layer above the capping layer and the first dielectric layer, wherein a portion of the memory layer is directly above the first dielectric layer, such that a top surface of the capping layer, a top surface of the first dielectric layer, and a bottom surface of the memory layer are substantially coplanar;
• forming a second dielectric layer above the first dielectric layer and the memory layer;
• and
• forming a top via in the second dielectric layer and above the memory layer.