Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array

A process for forming a transistor above a planar surface of a substrate, comprising:

• Providing first and second conductive layers comprising each a material that is suitable for the first and the second conductive layers to form a drain region and a source region of the transistor, respectively, the first and second conductive layers being isolated from each other by an isolation layer;
• providing an active layer in contact with both the first and second conductive layers, wherein the active layer comprises a material suitable for forming a channel region of the transistor and wherein a portion of the active layer is provided above either the first conductive layer or the second conductive layer;
• providing a gate dielectric layer over the active layer;
• providing a third conductive layer over gate dielectric layer;
• etching the active layer, the gate dielectric layer and the third conductive layer to form a line structure around the second conductive layer, the isolation layer and the first conductive layer;
• providing a passivation layer to enclose the third conductive layer, the gate dielectric layer, the first and the second conductive layers, the active layer, and the isolation layer;
• etching the passivation layer to provide a via to expose a portion of the second conductive layer or a portion of the first conductive layer;
• and
• providing a metallic layer on the exposed portion of second conductive layer or the exposed portion of the first conductive layer.