Semiconductor device, memory device, and method for forming transistor on substrate

A memory device, comprising:

• one or more memory cell transistors;
• and
• a peripheral circuit configured to control the memory cell transistors and including an NMOS (N-type Metal Oxide Semiconductor) transistor comprising:
• a gate insulating layer formed on a substrate,
• a stacked semiconductor layer including:
• a first layer formed on the gate insulating layer and including a phosphorus doped polycrystalline semiconductor,
• a second layer formed on the first layer and including a carbon-doped polycrystalline semiconductor, and
• a third layer formed on the second layer and including a phosphorus-doped or undoped polycrystalline semiconductor, and
• a metal layer on or above the stacked semiconductor layer, wherein the third layer includes less phosphorus than the first layer or does not include phosphorus.

A method for forming a transistor on a substrate, the method comprising:

• forming a gate insulating layer on the substrate;
• forming a stacked semiconductor layer that includes:
• a first layer including a phosphorus-doped polycrystalline semiconductor on the gate insulating layer,
• a second layer including a carbon-doped polycrystalline semiconductor on the first layer, and
• a third layer including a phosphorus-doped or undoped polycrystalline semiconductor on the second layer, wherein the third layer includes less phosphorus than the first layer or does not include phosphorus;
• and
• forming a metal layer on or above the third layer.