Three-dimensional semiconductor devices

A three-dimensional semiconductor memory device, comprising:

• first source conductive patterns on a substrate, the first source conductive patterns being spaced apart from each other in a first direction;
• second source conductive patterns on the first source conductive patterns, the second source conductive patterns being spaced apart from each other in the first direction;
• stacks on the second source conductive patterns, the stacks being spaced apart from each other in the first direction, and the stacks including a plurality of gate electrodes stacked on each of the second source conductive patterns;
• and
• vertical channel portions penetrating the stacks and the first and second source conductive patterns, each of the vertical channel portions being in contact with a side surface of each of the first source conductive patterns,
• wherein a distance between the first source conductive patterns adjacent in the first direction is a first width,
• wherein a distance between the second source conductive patterns adjacent in the first direction is a second width, and
• wherein the first width is larger than the second width.

A three-dimensional semiconductor memory device, comprising:

• a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral circuit transistors;
• a second substrate on the peripheral circuit structure;
• first source conductive patterns on the second substrate;
• second source conductive patterns on the first source conductive patterns;
• stacks on the second source conductive patterns, each of the stacks including a plurality of gate electrodes stacked on the second source conductive patterns;
• vertical channel portions penetrating the stacks and the first and the second source conductive patterns and extending into the second substrate, the vertical channel portions being in contact with a side surface of each of the first source conductive patterns;
• charge storing layers interposed between each of the vertical channel portions and each of the stacks;
• and
• a common source pattern interposed between the stacks, the common source pattern extended between the first source conductive patterns and between the second source conductive patterns,
• wherein a distance from the center line of the common source pattern to one of the first source conductive patterns is larger than a distance from the center line of the common source pattern to one of the second source conductive patterns.