US 11,910,605 B2Granted

Semiconductor storage device and method of manufacturing semiconductor storage device

AssigneeKioxia Corporation

InventorsGen Kuribayashi, Shigeki Kobayashi

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Abstract

A semiconductor storage includes a stack, columns, and first, second, third, fourth, and fifth insulators. The stack includes first conductive layers, and second and third conductive layers below and above the first conductive layers, respectively. The columns penetrate the stack in a first direction. The first and second insulators penetrate the stack and are separated from each other in a second direction. The third insulator is between the first and second insulators in a third direction. The third insulator includes first and second portions apart from each other in the second direction. The fourth insulator is between the first and second portions. The fifth insulator is between the first and second portions above the fourth insulator. The second conductive layer includes two electrically-separated regions, between which the third and fourth insulators are provided. The third conductive layer includes two electrically-separated regions between which the third and fifth insulators are provided.

Claims20

Dependent claims

A semiconductor storage device, comprising:

a stack including a plurality of first conductive layers stacked in a first direction, a second conductive layer disposed below the plurality of first conductive layers, and a third conductive layer disposed above the plurality of first conductive layers;
a plurality of first columns penetrating the stack in the first direction, each of the first columns including a semiconductor layer;
a first insulator penetrating the stack in the first direction and extending in a second direction intersecting the first direction;
a second insulator at a position separated from the first insulator in a third direction intersecting the first and second directions, the second insulator penetrating the stack in the first direction and extending in the second direction;
a third insulator between the first and second insulators in the third direction and penetrating the stack in the first direction and the third insulator extending in the second direction and including a first portion and a second portion that are spaced from each other in the second direction;
a fourth insulator between the first portion and the second portion and extending in the first and second directions;
and
a fifth insulator between the first portion and the second portion above the fourth insulator, and extending in the first and second directions, wherein
the second conductive layer includes two electrically-separated regions between which the third and fourth insulators are provided, and
the third conductive layer includes two electrically-separated regions between which the third and fifth insulators are provided.

7 more elements

A method of manufacturing a semiconductor storage device, the method comprising:

forming a first stack by stacking at least one sacrificial layer and at least one insulating layer in a first direction;
forming a first insulator penetrating the first stack and extending in a second direction intersecting the first direction;
forming a second stack by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers one by one on the first stack and the first insulator;
forming a plurality of first columns, each including a semiconductor layer and penetrating the second stack;
forming a first slit and a second slit penetrating the second stack and extending in the second direction;
forming a third slit penetrating the second stack and extending in the second direction between the first and second slits in a third direction intersecting the first and second directions, such that the third slit has two portions separated from each other in the second direction;
removing the sacrificial layers of the first and second stacks and forming a plurality of conductive layers in spaces left by removal of the sacrificial layers;
filling the first, second, and third slits with an insulating material to form second, third, and fourth insulators, respectively;
and
forming a fifth insulator penetrating an uppermost one of the conductive layers above the first insulator, such that the fifth insulator extends between two portions of the fourth insulator formed in the two portions of the third slit in the second direction.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/684,834Filed 2 Mar 2022
Priority: JP 2021-15100016 Sep 2021
Published: US 2023/0083091 A116 Mar 2023
Granted: 20 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Family

US 2023/0083091 A1Pre-grant publication · published 16 Mar 2023
US 11,910,605 B2This patent

From the US filing history. Foreign family members aren’t listed.

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