Semiconductor device and electronic system including the same

A semiconductor device, comprising:

• a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate and stacked in a staircase shape;
• a memory channel structure extending through the gate electrode structure, the memory channel structure including:
• a channel including:
• a first portion extending in the first direction on the substrate;
• and
• a second portion extending in the first direction on and contacting the first portion, a lower surface of the second portion having a width less than a width of an upper surface of the first portion;
• a charge storage structure on an outer sidewall of the channel;
• a filling pattern contacting an inner sidewall of the channel and having a pillar shape;
• and
• a pad on upper surfaces of the channel and the filling pattern, the pad contacting an inner sidewall of the charge storage structure;
• an etch stop layer on a sidewall of the gate electrode structure and contacting a dummy gate electrode of the gate electrodes, the dummy gate electrode including an insulating material, and the etch stop layer overlapping an upper portion of the first portion of the channel in a horizontal direction parallel to the upper surface of the substrate;
• contact plugs electrically connected to respective ones of the gate electrodes except for the dummy gate electrode;
• and
• first upper wirings electrically connected to the contact plugs and applying electrical signals thereto.

An electronic system, comprising:

• a controller;
• and
• a semiconductor device electrically connected to the controller through an input/output pad, the semiconductor device including:
• peripheral circuit wirings electrically connected to the input/output pad;
• and
• a memory cell structure electrically connected to the peripheral circuit wirings, the memory cell structure including:
• a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate and stacked in a staircase shape;
• a channel extending through the gate electrode structure, the channel including:
• a first portion extending in the first direction on the substrate;
• and
• a second portion extending in the first direction on and contacting the first portion, a lower surface of the second portion having a width less than a width of an upper surface of the first portion;
• a charge storage structure on an outer sidewall of the channel;
• and
• an etch stop layer on a sidewall of the gate electrode structure and contacting a dummy gate electrode of the gate electrodes, the dummy gate electrode including an insulating material, and the etch stop layer overlapping an upper portion of the first portion of the channel in a horizontal direction parallel to the upper surface of the substrate.