Stacked connections in 3D memory and methods of making the same

A memory device, comprising:

• a first layer stack having first alternating conductor and insulator layers;
• a top dielectric layer disposed on the first layer stack;
• a second layer stack, disposed over the top dielectric layer and having second alternating conductor and insulator layers;
• a first vertical structure extending through the first layer stack, wherein the first vertical structure comprises a first NAND string having a first memory layer;
• a second vertical structure extending through the second layer stack and at least a portion of the top dielectric layer, wherein the second vertical structure comprises a second NAND string having a second memory layer;
• and
• a conductive material sandwiched between the first vertical structure and the second vertical structure, wherein:
• the first memory layer comprises a first blocking layer, a first storage layer, a first tunneling layer and a first channel layer, wherein the first blocking layer, the first storage layer, the first tunneling layer and the first channel layer extend through the first layer stack;
• the second memory layer comprises a second blocking layer, a second storage layer, a second tunneling layer and a second channel layer, wherein the second blocking layer, the second storage layer, the second tunneling layer and the second channel layer extend through the second layer stack;
• a width of the conductive material is greater than a width of the first vertical structure and a width of the second vertical structure at interfaces contacting the conductive material;
• and
• a portion of the conductive material surrounds a bottom portion of the second vertical structure, wherein the portion of the conductive material that surrounds the bottom portion of the second vertical structure is in direct contact with the second layer stack and is coplanar with the top dielectric layer.