Capacitor and a DRAM device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKyooho Jung, Dongkwan Baek, Cheoljin Cho
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Abstract
A capacitor may include a lower electrode, a dielectric layer structure on the lower electrode, and an upper electrode on the dielectric layer structure. The dielectric layer structure may include a plurality of dielectric layers and at least one insert layer structure between ones of the plurality of dielectric layers. The insert layer structure may include a plurality of zirconium oxide layers and at least one insert layer. The insert layer may be between ones of the plurality of zirconium oxide layers. The capacitor may have a high capacitance and low leakage currents.
Claims16
A capacitor, comprising:
- a lower electrode;
- a dielectric layer structure on the lower electrode, the dielectric layer structure comprising a plurality of dielectric layers and at least one insert layer structure between ones of the plurality of dielectric layers;
- and
- an upper electrode on the dielectric layer structure,
- wherein the at least one insert layer structure includes a plurality of zirconium oxide layers and at least two insert layers, and each of the at least two the insert layers is between ones of the plurality of zirconium oxide layers, wherein the insert layer structure comprising at least two insert layers is higher than a central portion in a vertical direction of the dielectric layer structure.
A capacitor, comprising:
- a lower electrode;
- a dielectric layer structure on the lower electrode, the dielectric layer structure including a plurality of dielectric layers and a single insert layer structure between ones of the plurality of dielectric layers;
- and
- an upper electrode on the dielectric layer structure;
- wherein the single insert layer structure includes at least a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer stacked sequentially,
- wherein the dielectric layer structure includes a plurality of aluminum oxide layers,
- wherein the single insert layer structure includes the plurality of aluminum oxide layers spaced apart from each other and the single insert layer structure comprising the plurality of aluminum oxide layers is higher than a central portion in a vertical direction of the dielectric layer structure, and
- wherein a thickness of each of the plurality of aluminum oxide layers is less than a thickness of the first zirconium oxide layer and the second zirconium oxide layer and a sum of thicknesses of the aluminum oxide layers in the dielectric layer structure is 1 Å to 3 Å.
A DRAM device, comprising:
- a cell transistor on a substrate, the cell transistor including a gate structure, a first impurity region, and a second impurity region;
- a bit line structure electrically connected to the first impurity region;
- a capacitor on the bit line structure, the capacitor electrically connected to the second impurity region,
- wherein the capacitor comprises:
- a lower electrode;
- a dielectric layer structure on the lower electrode, the dielectric layer structure including a plurality of dielectric layers and at least one insert layer structure between ones of the plurality of dielectric layers, the dielectric layer structure having a thickness of 30 Å to 60 Å;
- and
- an upper electrode on the dielectric layer structure,
- wherein the at least one insert layer structure comprises at least a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer stacked sequentially, and
- wherein the dielectric layer structure includes a plurality of aluminum oxide layers,
- wherein the at least one insert layer structure comprises a single insert layer structure in the dielectric layer structure, and wherein the single insert layer structure includes the plurality of aluminum oxide layers spaced apart from each other and the single insert layer structure comprising the plurality of aluminum oxide layers is higher than a central portion in a vertical direction of the dielectric layer structure.
Dependencies are inferred from the claim text.