Memory cell and semiconductor memory device with the same

A semiconductor memory device, comprising:

• a substrate;
• an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a first source/drain region, a second source/drain region and a thin-body channel between the first source/drain region and the second source/drain region;
• a bit line extending in a direction vertical to the substrate and connected to the first source/drain region;
• a capacitor connected to the second source/drain region;
• and
• a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween,
• wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line, wherein
• the thickness of the thin-body channel is smaller than that of first source/drain region, and
• the thickness of the thin-body channel is equal to that of the second source/drain region.

A semiconductor memory device, comprising:

• a substrate;
• and
• a memory cell array including memory cells stacked along a direction vertical to the substrate,
• wherein each of the memory cells comprises:
• a bit line vertically oriented to the substrate;
• a capacitor laterally spaced apart from the bit line;
• an active layer laterally oriented between the bit line and the capacitor;
• and
• a word line disposed on an upper portion of the active layer and laterally oriented to intersect with the active layer,
• a bit line contact node disposed between one side of the active layer and the bit line;
• a bit line side-ohmic contact disposed between the bit line contact node and the bit line;
• a storage contact node disposed between another side of the active layer and the capacitor;
• and
• a storage node side-ohmic contact disposed between the storage contact node and the capacitor,
• wherein the active layer includes a thin-body channel, a thickness of the thin-body channel is smaller than a thickness of the word line.

A semiconductor memory device, comprising:

• a substrate;
• and
• a memory cell array including memory cells stacked along a direction vertical to the substrate,
• wherein each of the memory cells comprises:
• a bit line vertically oriented to the substrate;
• a capacitor laterally spaced apart from the bit line;
• an active layer laterally oriented between the bit line and the capacitor, and including a first source/drain region, a second source/drain region and a thin-body channel between the first source/drain region and the second source/drain region;
• a word line disposed on an upper portion of the active layer and laterally oriented to intersect with the active layer,
• wherein a thickness of the thin-body channel is smaller than a thickness of the word line, wherein
• a thickness of the thin-body channel is smaller than that of first source/drain region, and
• the thickness of the thin-body channel is equal to that of the second source/drain region.