Back to results
US 11,910,587 B2Granted
Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHidehiro Fujiwara, Yi-Hsin Nien, Hung-Jen Liao
Life of this patent
Estimating the term…
Abstract
An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.
Claims20
An apparatus comprising:
- a plurality of memory cells including at least a first memory cell and a second memory cell;
- a first write port comprising a plurality of first write access transistors formed within a first area and laid out in a first doping region of the first memory cell;
- and
- a first read port comprising a plurality of first read access transistors formed within a second area and laid out in a second doping region of the first memory cell, the first read port being separated from the first write port by a second write port of the second memory cell,
- wherein the second write port comprises a plurality of second write access transistors formed within a third area between the first area and the second area.
2 more elements
An apparatus, comprising:
- a first memory cell and a second memory cell, the first memory cell comprising:
- a first storage unit comprising n-type transistors formed in a first n-plus (NP) region and p-type transistors formed in a first p-plus (PP) region between the first NP region and a second NP region;
- a plurality of first write access transistors formed in the first NP region or in the first PP region;
- and
- a plurality of first read access transistors formed in the second NP region;
- wherein a first write port is laid out in the first NP region of the first memory cell and a first read port laid out in the second NP region of the first memory cell, the first read port being separated from the first write port by a second write port of the second memory cell.
3 more elements
An apparatus, comprising:
- a first memory cell comprising:
- a plurality of first write access transistors formed within a first area;
- and
- a plurality of first read access transistors formed within a second area;
- and
- a second memory cell comprising:
- a plurality of second write access transistors formed within a third area between the first area and the second area,
- wherein the first memory cell and the second memory cell are memory cells in adjacent rows of the same column.
5 more elements
Dependencies are inferred from the claim text.