Well pick-up region design for improving memory macro performance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Chuan Yang, Chang-Ta Yang, Ping-Wei Wang
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Abstract
Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.
Claims20
A semiconductor device, comprising:
- a circuit region;
- a well pick-up (WPU) region;
- a first well extending lengthwise along a first direction through the circuit region and into the WPU region;
- a second well extending lengthwise along the first direction through the circuit region and into the WPU region;
- and
- a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region,
- wherein the first well, the third well, and the second well are sequentially arranged along a second direction perpendicular to the first direction.
A memory device, comprising:
- a memory cell region;
- a first well pick-up (WPU) region;
- a second WPU region, wherein the first WPU region, the memory cell region, and the second WPU region are sequentially arranged along a first direction;
- and
- an n-type well disposed on the first WPU region, the memory cell region, and the second WPU region,
- wherein the n-type well has a first portion extending continuously from the first WPU region to the second WPU region along the first direction, a second portion disposed on the first WPU region and extending lengthwise along a second direction perpendicular to the first direction, and a third portion disposed on the second WPU region and extending lengthwise along the second direction, wherein the second portion and the third portion are disposed on two sides of the first portion, and wherein the first, second, and third portions are continuously connected.
A semiconductor device, comprising:
- a circuit region;
- a first well-pick up (WPU) region;
- a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type;
- and
- a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type,
- wherein a width of the first well in the circuit region is less than a width of the first well in the first WPU region, and wherein the second well surrounds the first well.
Dependencies are inferred from the claim text.