Efficient port reconfiguration

A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method, the method comprising:

• identifying a target port of a switch for reconfiguration based on one or more reconfiguration parameters indicating how a set of logical ports are generated from the target port;
• disabling the target port at a control plane of the switch, thereby disabling a respective feature provided to the target port from the control plane, wherein the control plane provides a set of features supported by the switch at a port-level granularity for facilitating operations of the switch;
• configuring forwarding hardware of the switch based on the one or more reconfiguration parameters to accommodate the set of logical ports;
• and
• in response to the reconfiguration of the target port being complete at the forwarding hardware, enabling a respective logical port at the control plane, thereby enabling one or more features for the logical port from the control plane.

A computer system, comprising:

• a processor;
• a memory device;
• a hardware module comprising forwarding circuitry;
• a reconfiguration logic block to identify a target port of a switch for reconfiguration based on one or more reconfiguration parameters indicating how a set of logical ports are generated from the target port;
• and
• a management logic block to disable the target port at a control plane of the switch, thereby disabling a respective feature provided to the target port from the control plane, wherein the control plane provides a set of features supported by the switch at a port-level granularity for facilitating operations of the switch;
• wherein the reconfiguration logic block is further to:
• configure the hardware module of the switch based on the one or more reconfiguration parameters to accommodate the set of logical ports;
• and
• in response to the reconfiguration of the target port being complete at the forwarding hardware, enabling a respective logical port at the control plane, thereby enabling one or more features for the logical port from the control plane.