Low jitter PLL

A Phase Locked Loop (PLL) with reduced jitter, the PLL comprising:

• a phase detector, for receiving a reference clock and a feedback clock, and comparing phases of the reference clock and feedback clock to generate up and down control signals;
• a Voltage Controlled Oscillator (VCO) for generating an oscillation signal according to the up and down control signals;
• an output divider, for dividing the oscillation signal to generate an output clock;
• and
• a feedback loop, for receiving the oscillation signal and dividing the oscillation signal according to a modulus to generate the feedback clock, the feedback loop comprising:
• a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock, wherein an average of the modulated sequence over a plurality of clock cycles is a fractional number;
• and
• a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock;
• wherein a frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and the divided clock is used as the feedback clock.